Title:
【発明の名称】半導体記憶装置
Document Type and Number:
Japanese Patent JP2842816
Kind Code:
B2
Abstract:
In a semiconductor memory including first and second bit lines complementary to each other and provided for each one memory cell column, and a sense amplifier connected to the first and second bit lines, for sensing and amplifying a voltage difference between the first and second bit lines, a first pull-up circuit is connected to the first bit line, for pulling up, in accordance with a potential of the second bit line, the first bit line to a high voltage supply potential. A second pull-up circuit is connected to the second bit line, for pulling up, in accordance with a potential of the second bit line, the second bit line to a high level potential lower than that the high voltage supply potential by a predetermined potential difference.
Inventors:
KAWAHARA HIROYASU
Application Number:
JP26692295A
Publication Date:
January 06, 1999
Filing Date:
October 16, 1995
Export Citation:
Assignee:
NIPPON DENKI AISHII MAIKON SHISUTEMU KK
International Classes:
G11C7/06; G11C7/12; G11C11/41; G11C11/419; (IPC1-7): G11C11/41; G11C7/00
Domestic Patent References:
| JP2183492A | ||||
| JP63306590A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)