Title:
【発明の名称】プロセッサシステムおよびデバックモード実現方法
Document Type and Number:
Japanese Patent JP2843152
Kind Code:
B2
Abstract:
A processor system switched between a normal operation mode without normal floating-point exception and a debug mode with normal floating-point exception. This processor system includes means for dispatching integer and floating-point commands, an integer unit equipped with a multi-stage integer pipeline for executing the integer command, a floating-point unit equipped with a multi-stage floating-point pipeline for executing the floating-point command, and means for switching the system between the normal operation mode and the debug operation mode. When the system is in the debug mode, the command is prevented from being processed until the system judges whether or not the floating-point command induces the exception after the floating-point command is dispatched, and the system is allowed to transmit the normal exception when it is out of the ordinary mode.
Inventors:
BURATSUTO JOZEFU PII
BURUNAN JON
HISU PIITAA YANTETSUKU
JOSHI CHANDORA ESU
HATSUFUMAN UIRIAMU EI
NOFUARU MONIKA AARU
ROTSUDOMAN PAURO
SUKANRON JOZEFU TEI
TAN MAN KITSUTO
BURUNAN JON
HISU PIITAA YANTETSUKU
JOSHI CHANDORA ESU
HATSUFUMAN UIRIAMU EI
NOFUARU MONIKA AARU
ROTSUDOMAN PAURO
SUKANRON JOZEFU TEI
TAN MAN KITSUTO
Application Number:
JP51666794A
Publication Date:
January 06, 1999
Filing Date:
December 15, 1994
Export Citation:
Assignee:
SHIRIKON GURAFUITSUKUSU INC
TOSHIBA KK
TOSHIBA KK
International Classes:
C11D1/62; D06M13/46; C11D1/645; C11D1/65; C11D1/835; C11D3/00; D06M13/02; D06M13/184; D06M13/188; D06M13/322; D06M13/463; G06F9/38; G06F11/36; C11D1/04; C11D1/72; D06M; (IPC1-7): G06F9/38; G06F9/38
Domestic Patent References:
| JP2181236A |
Attorney, Agent or Firm:
Hidekazu Miyoshi (1 outside)