Title:
【発明の名称】半導体記憶装置及びその製造方法
Document Type and Number:
Japanese Patent JP2856256
Kind Code:
B2
Abstract:
PURPOSE:To prevent information in a memory cell from being destroyed when a plate pulse method is applied and to reduce a power consumption by a method wherein counter electrodes of a storage capacity are separated at each memory cell group connected in common by a word line. CONSTITUTION:Storage electrodes 24 are formed longitudinally so as to be situated on word lines WL used to select their memory cell; counter electrodes 28 formed via thin insulating films 26 are formed longitudinally so as to be situated on the word lines WL and are separated into memory cell groups selected by one word line WL. That is to say, since the storage electrodes 24 are formed longitudinally on the word lines WL, they cannot come into direct contact with a drain region 16 of a transfer transistor; accordingly, an electrode extraction layer 30 is formed, and the drain region 16 of the transfer transistor Q is connected to the storage electrodes 24. When the counter electrodes 28 of a storage capacity are separated at each memory cell group in this manner, information in the memory cell is not destroyed even when a plate pulse method is applied; a power consumption for a charging operation and a discharging operation can be reduced.
Inventors:
EMA TAIJI
Application Number:
JP6000289A
Publication Date:
February 10, 1999
Filing Date:
March 13, 1989
Export Citation:
Assignee:
FUJITSU KK
International Classes:
G11C11/404; H01L21/8242; H01L27/10; H01L27/108; (IPC1-7): H01L27/108; H01L21/8242
Domestic Patent References:
| JP5870490A | ||||
| JP5848294A | ||||
| JP5862892A | ||||
| JP57120295A |
Attorney, Agent or Firm:
Kitano Yoshito