Title:
【発明の名称】数値制御発振器
Document Type and Number:
Japanese Patent JP2867134
Kind Code:
B2
Abstract:
PURPOSE:To increase the upper limit of a clock frequency more by dividing a conventinoal numerical control oscillator into plural numbers and decreasing the number of digits of an adder in each split numerical control oscillator to decrease the delay time required for addition of each adder. CONSTITUTION:A conventional N-bit adder AD is split into an N1 bit adder and an N2-bit adder, and an N-bit flip-flop FF is split into an N1-bit flip-flop and an N2-bit flip-flop respectively. That is, the numerical control oscillator is split to r sets of numerical control oscillators T1, T2...Tr-1, Tr and number of digits of addition of adders AD1, AD2...ADr-1, ADr is split into N1 and N2 bits smaller than the conventional N bits, then b1, b2...br-1, br from flip-flops FF1, FF>=2...FFr-1, FFr are inputted respectively to inputs B of the adders AD1, AD2...ADr-1, ADr and each delay time taddr until the result of addition is obtained clearly as an output C is decreased than the conventional delay time.
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Inventors:
HANEDA MUTSUO
Application Number:
JP24678984A
Publication Date:
March 08, 1999
Filing Date:
November 21, 1984
Export Citation:
Assignee:
NIPPON MUSEN KK
International Classes:
H03K3/02; H03K23/64; H03K23/66; (IPC1-7): H03K23/64
Domestic Patent References:
| JP60214632A | ||||
| JP5441376B2 |