Title:
【発明の名称】順序論理回路
Document Type and Number:
Japanese Patent JP2868613
Kind Code:
B2
Abstract:
A sequential logic circuit includes first, second and third state hold circuits (11, 12, 13), each having a first input terminal, a second input terminal and an output terminals. The first input terminal of the first state hold circuit receives a clock signal (C), and the second input terminal of the first state hold circuit and the first input terminal of the second state hold circuit receive a data signal (D). The second input terminal of the second state hold circuit receives an inverted clock signal corresponding to an inverted version (/C) of the clock signal. The output terminal of the first state hold circuit and the output terminal of the second state hold circuit are connected to the first and second input terminals of the third state hold circuit, respectively. An output signal of the sequential logic circuit is output via the output terminal of the third state hold circuit. Each of the first, second and third state hold circuits has the following truth table: where A and B are signals applied to the first and second input terminals, respectively, and Qn and Qn+1 are respectively signals obtained at the output terminal. The sequential logic circuit inputs the data signal only when the clock signal changes.
