Title:
【発明の名称】出力バッファ回路
Document Type and Number:
Japanese Patent JP2872058
Kind Code:
B2
Abstract:
An output buffer circuit is provided, which permits reduction of the delay of a digital output signal with respect to an input digital signal. The output buffer circuit (1) includes first and second FETs (11, 12) serially connected to each other. The gate of the first FET is applied with a first digital input signal (Sa). The gate of the second FET is applied with a second digital input signal (Sb). The first and second FETs operate to be opposite or complementary in logic state to each other. A digital output signal (Sc) is taken out from the connection point (16) of the first and second FETs. The circuit further includes a current source (13) for causing a bias current having the same direction or polarity as that of the drain current of the first FET to flow through the first FET in the pseudo-OFF state. The turn-on speed of the first FET from the pseudo-OFF state to the ON state is enhanced by the bias current.
Inventors:
INAMI DAIJIRO
SATO JUICHI
SATO JUICHI
Application Number:
JP31672594A
Publication Date:
March 17, 1999
Filing Date:
December 20, 1994
Export Citation:
Assignee:
MYAGI NIPPON DENKI KK
NIPPON DENKI KK
NIPPON DENKI KK
International Classes:
H03K17/687; H03K19/017; H03K19/0175; H03K17/04; (IPC1-7): H03K19/017; H03K17/04; H03K17/687; H03K19/0175
Domestic Patent References:
| JP57106234A |
Attorney, Agent or Firm:
Naoki Kyomoto