Title:
【発明の名称】半導体記憶装置
Document Type and Number:
Japanese Patent JP2874459
Kind Code:
B2
Abstract:
PURPOSE:To prevent the MOS transistor TR of a data output circuit from being broken even at the time when a supply voltage from the outside is high in the case of burn-in test or the like. CONSTITUTION:A reference voltage generating part 1 is provided which generates a reference voltage Vr in a certain level at the time when a supply voltage Vcc from the outside exceeds a prescribed level. A supply voltage comparing part 2, a switching part 3, and an internal power generating part 4 are provided which generate an internal supply voltage Vip which is equal to the supply voltage Vcc from the outside in the case of the supply voltage Vcc lower than a reference voltage Vr and is equal to the reference voltage Vr in the case of the supply voltage Vcc higher than the reference voltage Vr. The internal supply voltage Vip is used as the supply voltage of a data output circuit 5.
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Inventors:
HANNAI SEIICHI
Application Number:
JP17511592A
Publication Date:
March 24, 1999
Filing Date:
July 02, 1992
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
G11C11/413; G11C11/401; G11C11/407; G11C11/409; G11C29/00; G11C29/06; H01L21/822; H01L27/04; H01L27/10; (IPC1-7): G11C11/407; G11C11/401; G11C11/413; H01L21/822; H01L27/04; H01L27/10
Domestic Patent References:
| JP2210688A | ||||
| JP415949A | ||||
| JP417191A | ||||
| JP5717227A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)