Title:
【発明の名称】集積半導体メモリ
Document Type and Number:
Japanese Patent JP2875016
Kind Code:
B2
Abstract:
An integrated semiconductor memory includes a memory cell field having memory cells disposed in matrix form, word lines and internal bit lines forming pairs of internal bit lines for triggering the memory cells. Internal weighting circuits are each assigned to a respective one of the internal bit line pairs. An external pair of bit lines is commonly assigned to the internal bit lines. Pairs of separation transistors are each assigned to a respective one of the internal bit line pairs for electrical separation of the respective internal bit line pair from the external pair of bit lines. A bit line decoder triggers the pairs of separation transistors. An external weighting circuit is provided. A discriminator device and a precharging device are connected to the external bit line pair. The internal bit lines of each pair of internal bit lines are triggered separately from one another. The internal bit lines of each pair of internal bit lines are connected to the external bit line pair separately from one another.
Inventors:
HOFUMAN KURUTO
KOWARIIKU OSUKAA
KURAUSU RAINAA
RUSUTEITSUHI BERUNHARUTO
OBERURE HANSU DEIITAA
KOWARIIKU OSUKAA
KURAUSU RAINAA
RUSUTEITSUHI BERUNHARUTO
OBERURE HANSU DEIITAA
Application Number:
JP50194090A
Publication Date:
March 24, 1999
Filing Date:
January 22, 1990
Export Citation:
Assignee:
JIIMENSU AG
International Classes:
G11C11/401; G01R31/28; G11C11/4094; G11C11/4096; G11C29/00; G11C29/18; G11C29/34; (IPC1-7): G11C29/00; G01R31/28; G11C11/401
Domestic Patent References:
| JP63244400A |
Attorney, Agent or Firm:
Iwao Yamaguchi