Title:
【発明の名称】半導体記憶装置及びその製造方法
Document Type and Number:
Japanese Patent JP2886097
Kind Code:
B2
Abstract:
PURPOSE: To prevent the interference of signal between bit lines by forming a first intersection for forming a transfer transistor in the extending direction of word line and a second intersection for forming no transfer transistor sequentially and then forming a storage electrode on the word line and bit line through an insulation film. CONSTITUTION: A region for forming a transfer transistor is located between bit lines BL1 while a plurality of active regions, present in the extending direction of word lines WL3 WL4 , are arranged in zigzag, i.e. shifted alternately in the lateral direction from the extending direction of the word lines WL3 , WL4 . The word line passes sequentially through a first intersection for forming the transfer transistor and a second intersection for forming no transfer transistor. The word lines WL3 , WL4 are bent to detour the contact part between the bit line BL1 and an impurity diffusion layer 14 and the contact part between a storage electrode 20a and an impurity diffusion layer 13.
Inventors:
EMA TAIJI
Application Number:
JP26786494A
Publication Date:
April 26, 1999
Filing Date:
October 31, 1994
Export Citation:
Assignee:
FUJITSU KK
International Classes:
H01L27/108; H01L21/8242; (IPC1-7): H01L27/108; H01L21/8242
Domestic Patent References:
| JP59231851A |
Attorney, Agent or Firm:
Keizo Okamoto