Title:
【発明の名称】対数圧縮回路
Document Type and Number:
Japanese Patent JP2890381
Kind Code:
B2
Abstract:
A log compressing circuit is arranged so that the clamping level is independent of the amplification factor of a first transistor for amplifying input current. The log compressing circuit includes the first transistor for amplifying input current, a compressing diode for log-compressing the amplified current, a clamp voltage generating diode serving as a source for generating a clamping voltage, and a second transistor for clamping the log-compressed voltage if the voltage goes beyond a predetermined clamp voltage. The second transistor has the same form as the first transistor and provides a collector connected to a cathode of the clamp voltage generating diode. The constant current is supplied to the second transistor from a constant current source.
Inventors:
INAMORI MASANORI
MYAKE TOSHIHIDE
MYAKE TOSHIHIDE
Application Number:
JP36015091A
Publication Date:
May 10, 1999
Filing Date:
December 28, 1991
Export Citation:
Assignee:
SHAAPU KK
International Classes:
H03G11/02; H03G7/00; H03G11/04; (IPC1-7): H03G11/04; H03G7/00; H03G11/02
Domestic Patent References:
| JP58114618A | ||||
| JP58108814A | ||||
| JP5483744A | ||||
| JP6038909U |
Attorney, Agent or Firm:
Koji Onishi