Title:
【発明の名称】薄膜トランジスタおよびその製造方法
Document Type and Number:
Japanese Patent JP2894391
Kind Code:
B2
Abstract:
A thin film transistor (TFT) capable of reducing the leakage current on the occasion when the transistor is OFF and lowering the resistance of an interconnection layer connected to source/drain regions and a method of manufacturing the same are disclosed. In the thin film transistor, the length in the channel width direction of a polycrystalline silicon film 15 in junction parts 15c of a pair of source/drain regions 15b and a channel region 15a is smaller than the length in the channel width direction of polycrystalline silicon film 15 in source/drain regions 15b. Accordingly, the leakage current generated in junction parts 15c on the occasion when the TFT is OFF is reduced. In addition, it is unnecessary to reduce the length in the channel width direction of source/drain regions 15b, so that the resistance of an interconnection layer connected to source/drain regions 15b is lowered as compared to the conventional one.
Inventors:
MURAKISHI TAKEO
Application Number:
JP1400792A
Publication Date:
May 24, 1999
Filing Date:
January 29, 1992
Export Citation:
Assignee:
MITSUBISHI DENKI KK
International Classes:
H01L21/336; H01L21/822; H01L21/8244; H01L27/092; H01L27/11; H01L29/423; H01L29/78; H01L29/786; (IPC1-7): H01L29/786; H01L21/336; H01L21/8244; H01L27/11
Domestic Patent References:
| JP3101271A | ||||
| JP256966A | ||||
| JP61252667A | ||||
| JP25572A | ||||
| JP199261A | ||||
| JP61100967A | ||||
| JP61187274A | ||||
| JP60136259A | ||||
| JP63165A | ||||
| JP6284562A | ||||
| JP63258057A | ||||
| JP2272763A | ||||
| JP3102875A |
Attorney, Agent or Firm:
Fukami Hisaro (3 outside)