Title:
【発明の名称】電圧加算回路
Document Type and Number:
Japanese Patent JP2900995
Kind Code:
B2
Abstract:
A voltage adder/subtractor circuit is provided, which has an improved frequency characteristic and which is operable at a low supply voltage such as approximately 1.1 V. This circuit includes a first differential pair of emitter/source-coupled first and second transistors driven by a first constant current, and a second differential pair of emitter/source-coupled third and fourth transistors driven by a second constant current having a same current value as that of the first constant current. A third constant current source/sink serving as a common load for the second and third transistors is connected to the collector/drain of the second transistor and the coupled collector/drain and base/gate of the third transistor. The third constant current source/sink supplies/sinks a third constant current having a same current value as that of the first constant current. A first input voltage is differentially applied across bases/gates of the first and second transistors. A second input voltage is applied to a base/gate of the fourth transistor. An output voltage is derived from the base/gate of the third transistor.
Inventors:
KIMURA KATSUHARU
Application Number:
JP21722396A
Publication Date:
June 02, 1999
Filing Date:
August 19, 1996
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
G06G7/14; H01L21/822; H01L27/04; H03F3/45; (IPC1-7): G06G7/14; H01L21/822; H01L27/04; H03F3/45
Domestic Patent References:
| JP457179A | ||||
| JP836616A |
Attorney, Agent or Firm:
Yosuke Goto (1 person outside)