Title:
【発明の名称】IC試験装置の波形発生器
Document Type and Number:
Japanese Patent JP2916594
Kind Code:
B2
Abstract:
PURPOSE: To miniaturize a high speed logic gate circuit, working also as a variable delay device, by deciding next input edge signal and then supplying delay data corresponding to the result. CONSTITUTION: Inputted rate signals are counted (1R, 1F), and then deoded (2n, 2F) decode signals are inputted into one of FF3 R-6R and 3F-6F, respectively. Into these FF, rising and falling pattern data are inputted, and bath pattern data hold rate signals, by 4 cycles. Since none of both the pattern data is made enable in the same cycle, RSFF7A-7D holding data are referred to, and whether the next input edge signal is for rise or for fall is decided. And the two, for separate usage, are used as a single combined-use variable delay device 17, and both delay data are switched (16, 15), and the edge signals of combination pattern data of bath inputted (17). And, by delaying the amount corresponding to both delay data skews on both sides are compensated. Thus scale of a high speed logic gate circuit is reduced by half.
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Inventors:
NIWA HIROMASA
Application Number:
JP18780395A
Publication Date:
July 05, 1999
Filing Date:
June 30, 1995
Export Citation:
Assignee:
HITACHI DENSHI ENJINIARINGU KK
International Classes:
G01R31/3183; (IPC1-7): G01R31/3183
Domestic Patent References:
| JP59192982A | ||||
| JP63111480A | ||||
| JP222577A | ||||
| JP3216568A | ||||
| JP62168482U | ||||
| JP224633U |
Attorney, Agent or Firm:
Yoshihito Iizuka