Title:
【発明の名称】半導体集積回路装置
Document Type and Number:
Japanese Patent JP2918367
Kind Code:
B2
Abstract:
PURPOSE:To obtain a semiconductor integrated circuit device for a picture processing control which outputs a gradation binary signal whose reproducibility is satisfactory. CONSTITUTION:A first resolution compensating circuit 12, second resolution compensating circuit 13, and third resolution compensating circuit 14 whose resolution compensating intensity is different are independently provided for an image area separating processing, gradation binary processing, and simple binary processing from a correction image signal S11. Then, first, second, and third correction image signals S12, S13, and S14 for optimally operating the image area separating processing, gradation binary processing, and simple binary processing are respectively outputted from those circuits 12, 13, and 14. Thus, the binary signal enabling a pseudo halftone display can be reproducibly outputted.
Inventors:
TAKI YOICHIRO
Application Number:
JP26028791A
Publication Date:
July 12, 1999
Filing Date:
October 08, 1991
Export Citation:
Assignee:
MITSUBISHI DENKI KK
International Classes:
G06T5/00; G06T7/00; G06T7/40; H04N1/403; H04N1/409; H04N1/40; (IPC1-7): H04N1/403; G06T5/00; G06T7/00; H04N1/40; H04N1/409
Domestic Patent References:
| JP62186664A |
Attorney, Agent or Firm:
Shigeaki Yoshida (2 outside)