Title:
【発明の名称】クロック供給回路を備える半導体集積回路
Document Type and Number:
Japanese Patent JP2923882
Kind Code:
B2
Abstract:
A semiconductor integrated circuit incorporating therein a clock supply circuit drives a plurality of peripheral circuits using different frequency-divided clocks. In order to avoid enlargement of switching current there is provided a frequency-dividing circuit for dividing external clock supplied from a clock supply terminal, and a plurality of peripheral circuits which are operated by frequency-divided clocks. There is provided a first clock supply circuit which is capable of generating frequency-divided clock with the highest frequency among frequency-divided clocks required by the peripheral circuits, and a plurality of second clock supply circuits for generating frequency-divided clocks from frequency-divided clock of the first clock supply circuit. Wiring to connect the first clock supply circuit to second clock supply circuits becomes short, and the number of wiring is reduced. Therefore it becomes possible to reduce the switching current.
Inventors:
TERAUCHI YOJI
Application Number:
JP7950097A
Publication Date:
July 26, 1999
Filing Date:
March 31, 1997
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
G06F1/06; G06F1/10; H03K19/0175; G06F1/08; (IPC1-7): G06F1/10; G06F1/08; H03K19/0175
Domestic Patent References:
| JP581447A | ||||
| JP5911423A | ||||
| JP3186912A | ||||
| JP553681A | ||||
| JP683616A |
Attorney, Agent or Firm:
Suzuki Akio