Title:
【発明の名称】論理シミュレータ
Document Type and Number:
Japanese Patent JP2924222
Kind Code:
B2
Abstract:
PURPOSE:To shorten a circuit design period by providing a means storing trace information and a means tracing back the cause of the change of a signal based on trace information. CONSTITUTION:A simulation means 20 including an arithmetic processing means 21 inputted a series of input signals for a logic circuit model inputted from a data input data means 10, executing logical operation and outputting the input signals becoming the cause of the change in an output signal as trace information, a data output means 30 and an auxiliary storage means 40 are provided. The simulation means 20 includes a trace information storage means 22 and a trace back information generation/storage means 23 retrieving the cause of the change of the latest signal in the direction of the input terminal of the circuit based on the stored trace information and storing obtained trace back information. When the value of the signal on the circuit does not agree with an expected value, an event becoming the cause can be traced back and the circuit design period can be shortened.
Inventors:
GOTO KAZUNAGA
Application Number:
JP3939491A
Publication Date:
July 26, 1999
Filing Date:
February 07, 1991
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
G06F11/25; G06F11/26; G06F17/50; (IPC1-7): G06F17/50
Domestic Patent References:
| JP2105943A |
Attorney, Agent or Firm:
Naotaka Ide