Title:
【発明の名称】フレーム位相変換回路、クロスコネクト装置および受信装置
Document Type and Number:
Japanese Patent JP2962472
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To warrant time sequence between signals through a same transmission line by adopting a control method of a phase conversion buffer among plural signals in common, making a difference between a write address and a read address between buffers constant while no stuffing is made to the phase conversion buffer so as to transmit plural signals while keeping a frame phase difference. SOLUTION: A demultiplexer section 1 demultiplexes an STM-1 frame into three AU-32 and gives them to highways 32-34. A memory is divided into ES2-4 and buffers 11-13, and a clock signal is replaced in one memory. Then a phase comparator section 7 makes analog discrimination as to whether or not twice- reading or skipped reading of the ES to absorb wondering is to be executed, stuff bits are produced simultaneously in the AU-32#1-#3, stuffing is executed in post-stage buffers 11-13 and transmission is attained while arranging frame phases between the AU-32. Furthermore, independent frame phase conversion is attained for an input signal having an independent frame phase.
Inventors:
TAKATORI MASAHIRO
NAKANO YUKIO
ISHIDA KEIICHI
MORI TAKASHI
ASHI MASAHIRO
SUGANO TADAYUKI
UEDA HIROMI
NAKANO YUKIO
ISHIDA KEIICHI
MORI TAKASHI
ASHI MASAHIRO
SUGANO TADAYUKI
UEDA HIROMI
Application Number:
JP10079498A
Publication Date:
October 12, 1999
Filing Date:
April 13, 1998
Export Citation:
Assignee:
HITACHI SEISAKUSHO KK
NIPPON DENSHIN DENWA KK
NIPPON DENSHIN DENWA KK
International Classes:
H04J3/00; H04J3/06; H04J3/07; H04L7/00; H04L12/28; (IPC1-7): H04J3/06; H04J3/00; H04J3/07; H04L7/00; H04L12/28
Domestic Patent References:
| JP281527A | ||||
| JP2302136A | ||||
| JP3179830A | ||||
| JP63262938A | ||||
| JP63262939A |
Attorney, Agent or Firm:
Ogawa Katsuo