Title:
【発明の名称】集積回路型パワー半導体スイッチ
Document Type and Number:
Japanese Patent JP2967498
Kind Code:
B2
Abstract:
PCT No. PCT/DE93/01178 Sec. 371 Date Jun. 13, 1995 Sec. 102(e) Date Jun. 13, 1995 PCT Filed Dec. 8, 1993 PCT Pub. No. WO94/14195 PCT Pub. Date Jun. 23, 1994A semiconductor arrangement with a vertical power semiconductor switch and an integrated CMOS or bipolar circuit is provided, whereby the integrated CMOS or bipolar circuit is arranged on a semiconductor islet insulated from a first semiconductor material region by a buried insulating layer. The first semiconductor material region is included as a part of the structure of the power semiconductor switch. The buried insulating layer is surrounded by a second semiconductor material region arranged between it and the first semiconductor material region, the doping of which is the opposite of that of the first semiconductor material region. The second semiconductor region is coupled to the first semiconductor region by a circuit. This circuit does not directly connect the potential of the second semiconductor material region with the potential of the first semiconductor material region. The circuit limits the potential of the second semiconductor material region to values smaller than those capable of influencing the integrated circuit.
Inventors:
BOGUZEUIKUZU REMIGIUZU
Application Number:
JP51366194A
Publication Date:
October 25, 1999
Filing Date:
December 08, 1993
Export Citation:
Assignee:
HANNINGU EREKUTORONITSUKU GMBH UNTO CO
International Classes:
H01L21/762; H01L21/76; H01L21/8222; H01L21/8234; H01L27/02; H01L27/06; H01L27/08; H01L27/082; H01L27/088; H01L29/78; (IPC1-7): H01L29/78; H01L21/762; H01L27/08
Domestic Patent References:
| JP62213272A | ||||
| JP62183554A |
Attorney, Agent or Firm:
Maeda Hitoshi