Title:
【発明の名称】半導体記憶装置
Document Type and Number:
Japanese Patent JP2974252
Kind Code:
B2
Abstract:
The semiconductor memory device comprises a plurality of word lines (WL) and a plurality of bit lines (BL) intersected by the plurality of word lines, and a plurality of memory cells located at intersections of the word lines and the bit lines. Each of the memory cells comprises a capacitor for storing information and a transfer transistor for reading information from and writing information into the capacitor, the gate of the transfer transistor being connected to a word line, the source of the transfer transistor being connected through a bit line contact (Cb) to a bit line, the drain of the transfer transistor being connected through a storage capacitor contact (Cs) to the storage electrode of the capacitor. A memory cell pair is formed by two nearby memory cells having a common bit line contact, and a unit memory cell array has a configuration in which the word lines are not arranged orthogonally with respect to the bit lines. The direction of the word lines or the bit lines is parallel with one side of a semi-conductor chip on which the semiconductor memory device is arranged. The unit memory cell array is divided by a straight line parallel with one side of the unit memory cell array into portions the number of which is an integer multiple of two, and the divided memory cell array constitutes two identical halves which are mirror images of each other.
Inventors:
Tadashi Ema
Koichi Hashimoto
Koichi Hashimoto
Application Number:
JP7000690A
Publication Date:
November 10, 1999
Filing Date:
March 20, 1990
Export Citation:
Assignee:
富士通株式会社
International Classes:
G11C11/401; H01L21/8242; H01L27/10; H01L27/108; (IPC1-7): H01L27/108; H01L21/8242
Domestic Patent References:
| JP6367771A | ||||
| JP1179449A | ||||
| JP62169473A |
Other References:
【文献】日経マイクロデバイス 1989.3 pp.54~58
Attorney, Agent or Firm:
Kitano Yoshito