Title:
【発明の名称】電子部品試験装置
Document Type and Number:
Japanese Patent JP2975398
Kind Code:
B2
Abstract:
PURPOSE:To simulate the execution environment of a device to be measured(DUT) without giving the influence of the execution of a test on the load of a CPU by varying the function of a functional module by making a control instruction stored selectively synchronously reply to operating sequence. CONSTITUTION:The complicated local processing of the DUT at every pin can be performed by using a signal processor 23 with a signal measuring module controlled by a sequencer. Also, a signal from the module is pre-processed at the processor 23, and is fed back to a high-order sequencer and the CPU. Furthermore, it is programmed so that communication between the processors 23 can be performed by providing a dedicated bus, therefore, the output of the processor 23 can perform arithmetic processing with each other. Since the calculation processing of those processors 23 can be performed synchronizing with a clock source, the output and the operations of the processors can be predicted, which guarantees reproducibility. Therefore, it is possible to stably and accurately perform the simulation of the DUT in real environment.
Inventors:
HIWADA KYOYASU
GUNJI KEITA
GUNJI KEITA
Application Number:
JP14364090A
Publication Date:
November 10, 1999
Filing Date:
May 31, 1990
Export Citation:
Assignee:
NIPPON HYUURETSUTO PATSUKAADO KK
International Classes:
G01R31/316; H01L21/66; G01R31/28; (IPC1-7): G01R31/316; G01R31/28
Domestic Patent References:
| JP63215975A | ||||
| JP6070373A | ||||
| JP61239177A | ||||
| JP63148176A | ||||
| JP5616547Y2 |
Attorney, Agent or Firm:
Hideo Ueno