Title:
【発明の名称】可変遅延回路の測定回路
Document Type and Number:
Japanese Patent JP2976914
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To decrease the number of input circuits to be reduced as compared with the number of variable delay circuits at the time of confirming the operation thereof, which is difficult in prior art. SOLUTION: The measuring circuit for variable delay circuit comprises a variable delay circuit 1 including a lamp waveform generation circuit 5 and a reference voltage generation circuit 6, and a comparison circuit 2 including a comparator 3 with select function and a OR gate 4. A comparator 3 selected by a select signal SEL compares an internal reference voltage TEST0 with an external reference voltage ref and delivers the results to the OR gate 4 where the output from the comparators 3 are ORed and outputted to an external terminal TEST. If the potential is different between the TEST0 and the ref, a low or high level is outputted to the TEST otherwise an intermediate level is outputted. A comparators 3 not selected by the select signal SEL output a low level to the OR gate 4 regardless of the value of TEST0 and ref.
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Inventors:
IJIKA MASAO
Application Number:
JP5345397A
Publication Date:
November 10, 1999
Filing Date:
March 07, 1997
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
G01R31/28; G01R31/319; (IPC1-7): G01R31/28; G01R31/319
Domestic Patent References:
| JP621789A |
Attorney, Agent or Firm:
Wakabayashi Tadashi