Title:
【発明の名称】半導体集積回路及びその設計方法並びに半導体集積回路の設計プログラムを記録した記録媒体
Document Type and Number:
Japanese Patent JP2989586
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit for which a clock signal- generating circuit, etc., provided in the integrated circuit can be tested easily. SOLUTION: A select signal output circuit 10 is provided in a semiconductor integrated circuit. When '0' is inputted to the D-terminal of the circuit 10, the circuit 10 switches a selector 12 to a partial circuit 2 side and a scan FF(flip flop) 11 inputs the output of the partial circuit 2. At the time of conducting scan tests, a select signal of '0' or '1' value is inputted to the select signal output circuit 10 from a scan-in terminal 3 and further inputted to the selector 12. The selector 12 selects the partial circuit 2 side when the select signal is '0' or the clock signal of a clock signal generating circuit 9 when the select signal is '1'. The output of the partial circuit 2 or the clock signal of the clock signal generating circuit 9 inputted to the scan FF 11 is outputted to the outside from a scan-out terminal 8 through a scan path 20.
Inventors:
TAKEOKA SADAMI
Application Number:
JP20323198A
Publication Date:
December 13, 1999
Filing Date:
July 17, 1998
Export Citation:
Assignee:
MATSUSHITA DENKI SANGYO KK
International Classes:
G06F11/22; H01L21/822; H01L27/04; G01R31/28; (IPC1-7): G01R31/28; G06F11/22; H01L21/822; H01L27/04
Domestic Patent References:
| JP5122022A | ||||
| JP62169066A | ||||
| JP59180467A | ||||
| JP59175133A |
Attorney, Agent or Firm:
Hiroshi Maeda (2 outside)