Title:
【発明の名称】半導体装置
Document Type and Number:
Japanese Patent JP2991489
Kind Code:
B2
Abstract:
A semiconductor device including a semiconductor substrate 1 and at least one first column-shaped semiconductor layer 10 of a first channel type formed on semiconductor substrate 1 in order of first, second and third regions, and having a side surface. At least one second column-shaped semiconductor layer 11 of a second channel type is selectively laminated on first semiconductor layer 10 in order of first, second and third regions, and having a side surface. A gate insulation film 8 is formed on the side surfaces of first semiconductor layer 10 and second semiconductor layer 11. A gate electrode 9 is formed on the insulation film 8 extending to an external portion of first semiconductor layer 10. A first source layer 2 and first drain layer 4 are respectively formed in the first and third regions of first semiconductor layer 10. A second source layer 7 and second drain layer 5 are respectively formed in the first and third regions of semiconductor layer 11. An input terminal 14 is connected to gate electrode 9 to lead out to the exterior of first semiconductor layer 10. An output terminal 15 is connected to second drain layer 5 formed on and in low-resistance contact with first drain layer. A first power source terminal 16 is connected to first source layer 2 of first semiconductor layer 10, and a second power source terminal 17 is connected to second source layer 7.
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Inventors:
NITAYAMA AKIHIRO
SAKUI YASUSHI
SAKUI YASUSHI
Application Number:
JP34040090A
Publication Date:
December 20, 1999
Filing Date:
November 30, 1990
Export Citation:
Assignee:
TOSHIBA KK
International Classes:
H01L21/8238; H01L27/092; H01L29/423; H01L29/78; (IPC1-7): H01L21/8238; H01L27/092; H01L29/78
Domestic Patent References:
| JP63291458A | ||||
| JP2194561A | ||||
| JP62176157A |
Attorney, Agent or Firm:
Takehiko Suzue (3 outside)