Title:
【発明の名称】論理回路シミユレーシヨン用期待値抽出方法
Document Type and Number:
Japanese Patent JP3017504
Kind Code:
B2
Abstract:
PURPOSE:To easily determine a strobe point at the time of the setting of an expectation value for logic simulation by dividing each test cycle performing the logic simulation of a logic circuit into a large number of equal time blocks and setting an event block on the basis of the min. (max.) data of the delay times of all elements. CONSTITUTION:Min. value delay simulation and max. value delay simulation are executed using the test pattern prepared by test planning with respect to a planned logic circuit and the data of respective output signals of the execution results are stored in a file. A strobe point is searched from those result data to set the strobe point common to all of output signals and the expectation value of each signal at said point is extracted. Logic inspection is performed on the basis of the set strobe point and the extracted expectation value but, from this constitution, the expectation value preparing work in test planning accompanied by the planning of the logic circuit becomes simple and can be automated.
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Inventors:
Hideaki Nishi
Toshio Yamamoto
Toshio Yamamoto
Application Number:
JP12729289A
Publication Date:
March 13, 2000
Filing Date:
May 20, 1989
Export Citation:
Assignee:
株式会社リコー
International Classes:
G06F11/25; G06F11/26; G06F17/50; G01R31/28; (IPC1-7): G01R31/28; G06F11/25; G06F17/50
Attorney, Agent or Firm:
Takashi Ohsawa