Title:
【発明の名称】導電体層形成方法
Document Type and Number:
Japanese Patent JP3034318
Kind Code:
B2
Abstract:
PURPOSE:To prevent transfer of projected and recessed portions of rough surface polysilicon 16 onto a layer insulating film 14 at the time of etching the rough surface polysilicon 16. CONSTITUTION:After a resist pattern 17 is formed on a rough surface polysilicon 16, a flattening film 18 is formed by coating and deposition of polyvinyl alcohol or CF system plasma polymerization film. A flat insulating film 14 can be exposed by etching such film with the etching condition same as that for the polysilicon 16 and flattening film 18.
Inventors:
Nobuo Ozawa
Jun Kanamori
Jun Kanamori
Application Number:
JP3481391A
Publication Date:
April 17, 2000
Filing Date:
February 28, 1991
Export Citation:
Assignee:
Oki Electric Industry Co., Ltd.
International Classes:
H01L27/04; H01L21/822; H01L21/8242; H01L27/10; H01L27/108; (IPC1-7): H01L27/108; H01L21/822; H01L21/8242; H01L27/04
Attorney, Agent or Firm:
Kenji Ohnishi