Title:
【発明の名称】干渉検出回路
Document Type and Number:
Japanese Patent JP3036854
Kind Code:
B2
Abstract:
Interference in a high speed receive signal is effectively detected in a TDMA communications system wherein a plurality of time slots is provided within a TDMA frame. A comparator (50) is arranged to receive a first signal indicative of receive signal strength and a reference level signal. The comparator compares the magnitudes of the two signals applied thereto and outputs a comparison result signal. A delay circuit (52) is supplied with a second signal indicative of a time slot which is not in use and which delays the second signal by a predetermined time using a clock which is synchronized with the time slots of the TDMA frame. A gate circuit (54), preceded by the comparator and the delay circuit, is supplied with the outputs of the comparator and the delay circuit. The gate circuit (54) outputs a third signal which changes a logic level in the event that the strength of the first signal exceeds that of the reference level signal during the time slot which is not in use.
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Inventors:
Seiji Kondo
Koji Akahori
Koji Akahori
Application Number:
JP41345290A
Publication Date:
April 24, 2000
Filing Date:
December 21, 1990
Export Citation:
Assignee:
NEC
Ando Electric Co., Ltd.
Ando Electric Co., Ltd.
International Classes:
H04B1/10; H04B7/185; H04B7/26; H04B17/00; H04B17/29; H04B17/345; H04J3/00; (IPC1-7): H04B17/00; H04B1/10; H04J3/00
Attorney, Agent or Firm:
Naotaka Ide