Title:
【発明の名称】半導体装置及び半導体装置の故障解析方法
Document Type and Number:
Japanese Patent JP3060998
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide the failure analysis method for semiconductor device which leaves the trace of failure at the time of occurrence of the failure, specifies the failure by only an optical means without re-applying a current stress, and can specify the failure easily without increasing the size of damage of the failure. SOLUTION: Before completion of production of a semiconductor device, a high molecular film 2 with such properties as to absorb light so as to induce isomerization and cause a variation in molecular spectrum at isomerized positions is coated on the surface of a semiconductor chip 1. When the semiconductor device having the high molecular film 2 on the surface of the semiconductor chip comes out of order, the high molecular film 2 detects the isomerized position 5 by an optical detector means 6, and specifies the failure position 3 of the semiconductor device using the detected results.
Inventors:
Takeshi Funatsu
Application Number:
JP14786997A
Publication Date:
July 10, 2000
Filing Date:
June 05, 1997
Export Citation:
Assignee:
NEC
International Classes:
G01R31/302; H01L21/66; G01R31/26; (IPC1-7): G01R31/26; H01L21/66
Domestic Patent References:
| JP955408A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)