Title:
【発明の名称】デジタル信号プロセサ
Document Type and Number:
Japanese Patent JP3061895
Kind Code:
B2
Abstract:
An improved digital signal processor (DSP) architecture including several multiply/accumulate devices (M-UNIT 0-K) connected to the DSP bus through a delay line, means (10,11,16,18) for simultaneously operating said multiply/accumulate devices and means (18) for selectively storing accumulated values into a pre-assigned Dual-Port RAM area.
Inventors:
Belo Jean Paul
Galant Claude
Galant Claude
Application Number:
JP16753091A
Publication Date:
July 10, 2000
Filing Date:
June 13, 1991
Export Citation:
Assignee:
International Business Machines Corporation
International Classes:
G06F13/00; G06F7/544; G06F17/10; (IPC1-7): G06F17/10
Domestic Patent References:
| JP62221725A |
Foreign References:
Attorney, Agent or Firm:
Tsukio Okada (1 person outside)