Title:
【発明の名称】論理回路設計支援装置
Document Type and Number:
Japanese Patent JP3065671
Kind Code:
B2
Abstract:
PURPOSE:To realize a smaller circuit scale by designating a circuit element desired to be left and erasing the circuit element judged that any signal carrying route does not exist as to all the circuit elements inside a logic circuit. CONSTITUTION:Circuit data is read and the set S of the circuit element whose output is connected with the external output terminal of the logic circuit within the circuit elements inside the logic circuit is obtained in a device which realizes the logic design of the logic device such as LSI, in a computer as a supporting application program. All the circuit elements outputting to the input of the circuit element added in the aggregation S are added to the aggregation S and the processing is repeated till the circuit element to be added is out. The set S finally becomes the set of the circuit element being logically necessary in the logic circuit. Therefore, all the circuit elements which are not added to the set S are erased from the logic circuit and circuit data is outputted. Thus, the smaller circuit scale is realized by correctly judging the necessity or unnecessity of the circuit element.
Inventors:
Hiroshige Fujii
Application Number:
JP215991A
Publication Date:
July 17, 2000
Filing Date:
January 11, 1991
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G06F17/50; (IPC1-7): G06F17/50
Domestic Patent References:
| JP382159A | ||||
| JP2285433A | ||||
| JP1205274A | ||||
| JP63282571A |
Attorney, Agent or Firm:
Hidekazu Miyoshi