Title:
【発明の名称】スーパースカラ・プロセッサの電力消費を減少させる回路及び方法
Document Type and Number:
Japanese Patent JP3072705
Kind Code:
B2
Abstract:
An enhanced microprocessor (278) (FIG. 6) having a first portion (153) (FIG. 7) and a second portion (196) (FIG. 8) configured to eliminate prefetching of instructions from an instruction cache (102) (FIG. 6) when the required instructions are already present within a prefetch buffer (104) (FIG. 6). The first portion (153) and second portion (196) are in circuit communication with a prefetch buffer (104) (FIG. 6), branch target cache (108) (FIG. 6), control unit (110) (FIG. 6), and execution unit (112) (FIG. 6). The first portion (153) is responsive to forward or backward branch instructions that have a branch target within the same prefetch buffer, and to forward branch instructions that have a branch target within a next successive prefetch buffer. The first portion (153) is configured to inhibit prefetching of instructions when such conditions are present. The second portion (196) is responsive to backward branch instructions that have a branch target within an immediately preceding prefetch buffer and configured to assert a prefetch inhibit signal to prevent any further prefetching of instructions.
Inventors:
Gavy Jay Salem
Terry Lee Weekley
Terry Lee Weekley
Application Number:
JP18686295A
Publication Date:
August 07, 2000
Filing Date:
July 24, 1995
Export Citation:
Assignee:
International Business Machines Corporation
International Classes:
G06F9/38; (IPC1-7): G06F9/38
Domestic Patent References:
| JP490027A | ||||
| JP4333929A | ||||
| JP4293124A |
Other References:
【文献】米国特許5623615(US,A)
Attorney, Agent or Firm:
Hiroshi Sakaguchi (1 person outside)