Title:
【発明の名称】基準電位発生回路
Document Type and Number:
Japanese Patent JP3076097
Kind Code:
B2
Abstract:
A reference potential generating circuit includes a plurality of MOS field effect transistors and a reference potential driver circuit. The MOS field effect transistors have different threshold voltages and a reference potential is obtained by amplifying the threshold voltage difference of the MOS field effect transistors. During the period in which a power supply potential externally supplied is lower than a predetermined target value of the reference potential, the reference potential driver circuit drives an output terminal for producing a potential corresponding to the power supply potential supplied externally. In this reference potential generating circuit, the S/N ratio is good and the circuit operation is stable, and is effective for reducing the power consumption and for increasing the integration density in semiconductor integrated circuit devices.
Inventors:
Koji Koshikawa
Naohiko Sugibayashi
Naohiko Sugibayashi
Application Number:
JP21254391A
Publication Date:
August 14, 2000
Filing Date:
August 26, 1991
Export Citation:
Assignee:
NEC
International Classes:
G11C11/413; G11C11/407; H01L21/822; H01L27/04; H03K17/22; H03K17/00; (IPC1-7): G11C11/413; H01L21/822; H01L27/04
Domestic Patent References:
| JP6376007A | ||||
| JP3131916A | ||||
| JP2230305A | ||||
| JP2122315A | ||||
| JP63229509A | ||||
| JP270264A | ||||
| JP59135520A | ||||
| JP317714A | ||||
| JP1129769A |
Attorney, Agent or Firm:
Naoki Kyomoto