Title:
【発明の名称】CMOSスタティックメモリセル
Document Type and Number:
Japanese Patent JP3082772
Kind Code:
B2
Abstract:
PURPOSE:To reduce a cell area per memory cell and enhance integration degree of the circuit as a whole, by forming a memory cell by dividing it into three layers and then arranging two MOS transistors of the same conductivity type to each layer. CONSTITUTION:A couple of N-channel MOS transistors for drive N1, N2 are formed for one memory cell of the first layer, the entire part of first layer is covered with an insulating film and contacts C1, C2 are formed. Next, a silicon single crystalline layer is stacked as the second layer, a couple of load type P-channel MOS transistors P1, P2 are then formed for the one memory cell, the entire part of the second layer is covered with an insulating layer and then contacts C3, C4, C7 and C8 are formed. Thereafter, a silicon single crystalline layer is stacked as the third layer, a couple of N-channel MOS transistors for transfer N3, N4 are formed for the one memory cell. In this case, a word line W is arranged and the entire part of the third layer is covered with an insulating layer an contacts C5, C6 are formed. Next, a desired MOS static RAM can be obtained by forming the digit lines D1, D2.
Inventors:
Shoichi Soeda
Application Number:
JP13737790A
Publication Date:
August 28, 2000
Filing Date:
May 28, 1990
Export Citation:
Assignee:
NEC
International Classes:
G11C11/412; H01L21/8244; H01L27/11; (IPC1-7): H01L21/8244; G11C11/412; H01L27/11
Domestic Patent References:
| JP3148168A | ||||
| JP3241773A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)