Title:
チップの封入構造
Document Type and Number:
Japanese Patent JP3107385
Kind Code:
U
Abstract:
A miniaturized chip scale package is provided for the improvement of conventional chip package issues such as bulky packaged volume and bad heat dissipation. This invention provides a leadframe comprising multiple block leads for semiconductor die attachment. Conducting metallic wires are used to connect all the block leads of the leadframe to the chip, then the metallic conducting wire part is specifically encapsulated with insulating material to further form a miniaturized encapsulated body. The encapsulated body fully enclose the wire bonding part and at least an out-connecting electrical conducting part is preserved on the lower part of the lead such that the final packaged volume is reduced, heat dissipation efficiency is enhanced, and the chip transfer speed to the outside is enhanced due to a reduction in the transfer distance by the rectangular block leads structure design.
Inventors:
Consecutive
Application Number:
JP2004005087U
Publication Date:
February 03, 2005
Filing Date:
August 25, 2004
Export Citation:
Assignee:
Honglian International Technology Co., Ltd.
International Classes:
H01L23/10; H01L23/31; H01L23/495; (IPC1-7): H01L23/28
Attorney, Agent or Firm:
Susumu Ito