Title:
【発明の名称】半導体集積回路
Document Type and Number:
Japanese Patent JP3138045
Kind Code:
B2
Abstract:
PURPOSE:To realize the high speed operation of a flip-flop circuit with a diagnostic function of the master slave system having no limit in the logic design in the normal operation. CONSTITUTION:A number of series connection stages of built-in gates of a bypass circuit BP connected in parallel with a series path circuit comprising 1st and 2nd storage circuits MF, SF is smaller than that of a storage circuit and an information transmission delay up to an input data output terminal 21 is smaller than the storage circuit. Thus, when data fed to a data input terminal 20 are fetched synchronously with a clock signal CK, before the output of the storage circuit is confirmed, the bypass circuit BP outputs the information to the output terminal. The 1st and 2nd storage circuits MF, SF are in master slave operation in the diagnostic mode and the output operation of the bypass circuit BP is suppressed corresponding to the state of signals MC1, MC2 to be controlled independently of the clock change in the 1st control signal CK and the master slave operation of the 1st and 2nd storage circuits MF, SF is warranted in the diagnostic mode.
Inventors:
Toshiro Takahashi
Kazuo Koide
Kazuo Koide
Application Number:
JP2198492A
Publication Date:
February 26, 2001
Filing Date:
January 10, 1992
Export Citation:
Assignee:
株式会社日立製作所
International Classes:
G06F11/22; G06F15/78; H03K3/037; H03K3/356; G01R31/28; (IPC1-7): H03K3/037; G01R31/28; G06F11/22; G06F15/78
Attorney, Agent or Firm:
Tamamura Shizuyo