Title:
【発明の名称】半導体装置の製造方法
Document Type and Number:
Japanese Patent JP3141805
Kind Code:
B2
Abstract:
To provide a fabrication method of compound semiconductor devices which can improve the problems of conventional MESFETs, such as the breakdown voltage degradation owing to increase of the gate leak current or the electron traps in the passivation film, the drain current decrease because of the gate-lag, or the threshold voltage dispersion caused by the interfacial tension, and easily restrain the emitter-size effect of conventional mesa type HBT without revising or complicating its epitaxial layer structure, a fabrication method according to the invention of a semiconductor device having a high-resistance film (9) covering a part of a surface other than electrodes (5, 6, and 7) of the semiconductor device comprises a step of depositing the high-resistance film (9) by way of catalytic CVD. The fabrication method preferably further comprises a step of surface cleaning performed before the step of depositing for cleaning the surface of the semiconductor device by a gas including active hydrogen flowing on the surface. As for the high-resistance film, a material including no oxygen such as SiN is applied.
Inventors:
Yousuke Miyoshi
Application Number:
JP764897A
Publication Date:
March 07, 2001
Filing Date:
January 20, 1997
Export Citation:
Assignee:
NEC
International Classes:
C23C16/34; H01L21/318; H01L21/331; H01L21/338; H01L29/205; H01L29/737; H01L29/73; H01L29/778; H01L29/812; H01L21/314; (IPC1-7): H01L21/318; H01L21/331; H01L21/338; H01L29/205; H01L29/73; H01L29/778; H01L29/812
Domestic Patent References:
| JP1083988A | ||||
| JP8250438A |
Attorney, Agent or Firm:
Naka Kanno