Title:
【発明の名称】半導体装置
Document Type and Number:
Japanese Patent JP3185220
Kind Code:
B2
Abstract:
There are a transistor (TR) comprising a gate electrode (23), a source region (24) and a drain region (25), and the structural body of a ferroelectric capacitor (C) on a local oxide film (26). This structural body has a ferroelectric film (29) sandwiched between an upper electrode (32) and a lower electrode (28). The upper electrode (32) and the source region (24) are connected by a wiring in which a conductive film (35) for preventing reactions and a wiring electrode (34) comprising Al are deposited. The conductive film (35) for preventing reactions is of TiN, MoSi, W or the like. Even when, after forming the wiring electrode, for the purpose of improving characteristics, an annealing treatment is performed or a final protective film is formed, the wiring electrode (34) does not react with the upper electrode (32), and a good ferroelectric film characteristic is obtained, and further, a ferroelectric memory of high performance and highly dense integration can be formed.
More Like This:
| JPH02282996 | REFERENCE CELL FOR READING EEPROM MEMORY ELEMENT |
| JP2011009409 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE |
| JP3392604 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE |
Inventors:
Kazuhiro Takeuchi
Application Number:
JP51529791A
Publication Date:
July 09, 2001
Filing Date:
September 26, 1991
Export Citation:
Assignee:
Seiko Epson Corporation
International Classes:
H01L27/115; (IPC1-7): H01L27/105
Domestic Patent References:
| JP2183569A | ||||
| JP2151060A | ||||
| JP3136361A | ||||
| JP4221848A |
Attorney, Agent or Firm:
Kisaburo Suzuki (1 outside)