Title:
【発明の名称】検査方法及び回路
Document Type and Number:
Japanese Patent JP3190364
Kind Code:
B2
Abstract:
A method for testing a systolic array in which a plurality of sequential registers is each connected to the rest by an intervening logic component. Each register includes a plurality of memory elements. Each register can be enabled to act as a latch register whereby digital data is loaded into an output therefrom in parallel or as a shift register whereby digital data is shifted sequentially in each register from one memory element to the next adjacent memory element. A test vector consisting of a preselected string of digital data is shifted in parallel into each of the registers. The test vector in each register is loaded into the associated logic component which operates on the vector and stores the data in the next adjacent register. The resulting data is serially clocked from each register onto unique bus nodes and examined in parallel to determine whether or not the expected result was obtained.
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Inventors:
Daryl E. Anderson
Ralph H. Lanham
Neil Sea Yarsma
Ralph H. Lanham
Neil Sea Yarsma
Application Number:
JP7473591A
Publication Date:
July 23, 2001
Filing Date:
March 14, 1991
Export Citation:
Assignee:
AGILENT TECHNOLOGIES, INC.
International Classes:
G01R31/28; G01R31/3185; G06F11/22; G11C29/00; G01R31/317; G11C29/02; G11C29/56; (IPC1-7): G01R31/317; G01R31/28; G06F11/22; G11C29/00
Domestic Patent References:
| JP1307853A |
Attorney, Agent or Firm:
Kimihisa Kato