Title:
【発明の名称】3レベル静電潜像をトナーで現像する方法及びその装置
Document Type and Number:
Japanese Patent JP3202746
Kind Code:
B2
Abstract:
The operating latitude of the tri-level xerographic process is improved by replacing the standard DC bias that is applied to one or both of the developer housings in conventional tri-level imaging with a chopped DC (CDC) developer bias. Chopped DC biasing is the alternate application of two discrete bias voltages to a developer stucture in a periodic fashion at a given frequency, with the period of each cycle divided up between the two bias levels at a duty cycle of from 5%-10% or 90%-95% depending upon which of the two developer structures is being biased. In the case of the DAD developer structure the duty cycle of higher of the two biases is 5%-10% and in case of a CAD developer structure the duty cycle of higher of the two biases is 90%-95%.
Inventors:
Richard Pegermain
James E Williams
James E Williams
Application Number:
JP31012990A
Publication Date:
August 27, 2001
Filing Date:
November 15, 1990
Export Citation:
Assignee:
Xerox Corporation
International Classes:
G03G13/01; G03G15/01; G03G15/06; G03G15/08; (IPC1-7): G03G15/01; G03G15/06
Domestic Patent References:
| JP1189663A | ||||
| JP6456462A | ||||
| JP61110162A | ||||
| JP61239253A | ||||
| JP61239254A |
Attorney, Agent or Firm:
Minoru Nakamura (7 outside)