Title:
【発明の名称】クロック信号を同期させる装置および方法
Document Type and Number:
Japanese Patent JP3220715
Kind Code:
B2
Abstract:
The method of synchronizing a sampling clock signal to a received data signal, the clock recovery circuit generates several clock signals at the symbol rate, with each clock signal having a unique phase. To permit fast initial acquisition, the set of clock signals includes a pair of clocks which differ in phase by one-half of a symbol interval. Additionally, the clock recovery circuitry generates error signals representing the difference between the phase of the received data signal and the phase of each clock signal. The error signals are processed over multiple symbol times to determine the optimal sampling phase. The clock recovery circuit then adjusts or maintains the phase of the symbol clock to provide the optimal sampling phase.
Inventors:
La Rosa, Christopher Pee
Kearney, Michael Jay
Baker, James Sea
Kearney, Michael Jay
Baker, James Sea
Application Number:
JP51652693A
Publication Date:
October 22, 2001
Filing Date:
January 21, 1993
Export Citation:
Assignee:
MOTOROLA INCORPORATED
International Classes:
H04B7/26; H04J3/06; H04L7/00; H04L7/033; H04L27/22; (IPC1-7): H04L27/22; H04B7/26; H04J3/06; H04L7/00
Other References:
１９９１電子情報通信学会春季全国大会講演論文集、分冊２ Ｐ．２−３６２（１９９１−３−１５）
Attorney, Agent or Firm:
Masanori Honjo (1 person outside)