【発明の名称】受信多値データ信号における高速データ検出およびクロック回復

Title:

【発明の名称】受信多値データ信号における高速データ検出およびクロック回復

Document Type and Number:

Japanese Patent JP3270894

Kind Code:

B2

Abstract:

An arrangement for high speed data detection and clock recovery in a multi-level data signal is disclosed wherein the received signal wavform is sampled at periodic preselected locations and the samples so obtained are compared to set values representing the expected levels at those locations. In within a permitted tolerance range over a given window of time, an indication of the presence of data is determined. Futher, if such correlation is determined to occur at a periodic rate, symbol-timing (clock) recovery is also indicated. A further embodiment with a dual recovery capability is also disclosed and described.

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Inventors:

McConnell, Peter Robert Henderson

Application Number:

JP50622992A

Publication Date:

April 02, 2002

Filing Date:

January 22, 1992

Export Citation:

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Assignee:

MOTOROLA INCORPORATED

International Classes:

H04L7/02; H04L7/033; H04L25/49; H04L27/14; H04L27/156; (IPC1-7): H04L7/02; H04L25/49; H04L27/14

Domestic Patent References:

JP62171338A
JP5789362A
JP62241450A

Attorney, Agent or Firm:

Shinsuke Onuki (1 person outside)

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