Title:
【発明の名称】データ処理システムにおける通信バス制御装置およびバス制御方法
Document Type and Number:
Japanese Patent JP3284311
Kind Code:
B2
Abstract:
A data processing sytem (10) having a direct memory access controller (DMAC) (12) which can be interrupted with a priortized signal to vary bus mastership of a communication bus (14) in the system. A prioritized interrupt signal is sent to a CPU (11) when the DMAC has bus mastership. The CPU only informs the DMAC of the highest priority cumulative interrupt priority. With the use of a mask value, the interrupt may be selectively screened by the DMAC so that selective interrupts may remove bus mastership from the DMAC.
Inventors:
Bradley Gene Burgess
James Bradley Eifalt
John Philip Dunn
James Bradley Eifalt
John Philip Dunn
Application Number:
JP41819390A
Publication Date:
May 20, 2002
Filing Date:
December 26, 1990
Export Citation:
Assignee:
MOTOROLA INCORPORATED
International Classes:
G06F13/34; G06F13/28; (IPC1-7): G06F13/34
Domestic Patent References:
| JP1206446A | ||||
| JP5916035A | ||||
| JP60239855A | ||||
| JP6115259A | ||||
| JP2193245A |
Attorney, Agent or Firm:
Shinsuke Ohnuki
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