Title:
【発明の名称】金属間化合物バリア層を有しプラチナを含有しない強誘電性メモリセル、およびその製造法
Document Type and Number:
Japanese Patent JP3285036
Kind Code:
B2
Abstract:
A ferroelectric memory cell integrated on a silicon substrate. The ferroelectric stack includes a ferroelectric layer, such as PbNbZrTiO, sandwiched between conductive metal-oxide electrodes, such as the perovskite LaSrCoO. The ferroelectric stack is grown over a barrier layer of an intermetallic alloy such as Ni3Al or Ti3Al, which is highly resistant to oxidation at elevated temperatures. The intermetallic layer is either deposited directly over the silicon substrate or over an intermediate TiN layer. The resulting structure does not require a platinum barrier layer.
Inventors:
Dote, Anil, M.
Ramesh, Rama Moore Sea
Ramesh, Rama Moore Sea
Application Number:
JP52522297A
Publication Date:
May 27, 2002
Filing Date:
December 17, 1996
Export Citation:
Assignee:
Bell Communications Research, Inc.
University of Maryland at College Park
University of Maryland at College Park
International Classes:
H01L21/02; H01L21/822; H01L21/8242; H01L21/8246; H01L21/8247; H01L27/04; H01L27/10; H01L27/105; H01L27/108; H01L29/788; H01L29/792; H01L29/92; (IPC1-7): H01L27/105; H01L21/822; H01L27/04
Domestic Patent References:
| JP555514A | ||||
| JP567792A | ||||
| JP8250680A |
Attorney, Agent or Firm:
Yoshikazu Tani (3 others)