Title:
【発明の名称】半導体記憶装置
Document Type and Number:
Japanese Patent JP3315293
Kind Code:
B2
Abstract:
A semiconductor memory device comprises a plurality of word lines (WL), a plurality of bit lines (BL) intersecting the word lines, and memory cells (M) selectively arranged at intersections of the word lines and the bit lines, and each consisting of a transistor and a capacitor (C), the transistor having a gate thereof connected to a corresponding one of the word lines, a drain thereof connected to a corresponding one of the bit lines, and a source thereof connected to an end of the capacitor and serving as a memory node, the capacitor having another end thereof connected to a plate electrode. In the semiconductor memory device, in an active mode assumed when a power supply is in an on state, that transistor of a memory cell which is connected to a selected one of the word lines is turned on, and those transistors of the other memory cells which are connected to non-selected word lines are in an off state. Further, in a standby mode assumed when the power supply is in the on state, when the power supply is in an off state, and when the power supply is turned on and off, the transistors of all the memory cells are in an off state.
Inventors:
Daizaburo Takashima
Yukihito Owaki
Yukihito Owaki
Application Number:
JP13685795A
Publication Date:
August 19, 2002
Filing Date:
June 02, 1995
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G11C11/405; G11C11/4074; G11C11/4076; G11C11/408; G11C11/4094; G11C14/00; H01L21/8242; H01L21/8247; H01L27/105; H01L27/108; H01L29/788; H01L29/792; (IPC1-7): G11C11/405
Attorney, Agent or Firm:
Takehiko Suzue