【発明の名称】トランジスタおよびその製造方法

Japanese Patent JP3323514

B2

The present invention relates to a transistor and a fabrication method thereof, and in particular, it relates to a technique for compatibly improving reduction of an ON-state voltage and reduction of a turn-off time. First and second emitter layers 4, 5 are selectively formed in isolation from each other on a surface of a base layer 3, and a channel region 6 opposed to a gate electrode 8 through a gate insulating film 7 is formed therebetween. In an ON state, a base current Ib is supplied from a base electrode 11, while a prescribed gate voltage is applied to the gate electrode 8. The first and second emitter layers 4 and 5 couple with each other and function as a single emitter layer, whereby the ON-state voltage becomes a low value of about the same degree as a bipolar transistor. When bringing a device into an OFF state, supply of the base current Ib is stopped while a zero (or negative) voltage is applied to the gate electrode 8. Consequently, coupling between the first emitter layer 4 and the second emitter layer 5 is canceled, whereby a second collector current Ic2 which is a component of a main current passing through the second emitter layer 5 rapidly attenuates similarly to a MOS.

JP3074736	[Title of Invention] Semiconductor device
JP4572541	Manufacturing method of semiconductor devices
JP2005503021	Edge termination of MOS transistor

Hideki Takahashi

JP51245398A

September 09, 2002

September 06, 1996

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Mitsubishi Electric Corporation

H01L29/739; (IPC1-7): H01L29/78

JP5190561A
JP6185866A
JP59149056A

Shigeaki Yoshida (2 outside)

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