Title:
【発明の名称】MOSトランジスタにおいてセルフアラインソース/ドレインコンタクトを形成する方法
Document Type and Number:
Japanese Patent JP3324702
Kind Code:
B2
Abstract:
A process for forming an MOS transistor with self-aligned contact holes comprises first forming a conductive layer of material over the substrate followed by formation of a capping layer of oxide over the conductive layer. The conductive layer and capping oxide layer are then patterned to form the gate electrode of a transistor with source/drain regions defined on either side thereof. A conformal layer of oxide is then disposed over the substrate and anisotropically etched to remove the oxide layer from the horizontal surfaces leaving a sidewall oxide layer on all substantially vertical surfaces. Thereafter, a second layer of conductive material is deposited over the substrate and patterned to form contacts.
Inventors:
Tu Chu Chan
You Pin Han
You Pin Han
Application Number:
JP7164289A
Publication Date:
September 17, 2002
Filing Date:
March 23, 1989
Export Citation:
Assignee:
SGS Thomson Microelectronics Ink.
International Classes:
H01L29/78; H01L21/28; H01L21/285; H01L21/336; H01L21/768; H01L21/8238; H01L21/8244; H01L27/092; H01L27/11; (IPC1-7): H01L21/8238; H01L21/28; H01L21/336; H01L21/768; H01L27/092; H01L29/78
Domestic Patent References:
| JP60194570A | ||||
| JP6010678A | ||||
| JP6197961A | ||||
| JP62219542A |
Attorney, Agent or Firm:
Takashi Koshiba