Title:
【発明の名称】データ受信制御装置
Document Type and Number:
Japanese Patent JP3349821
Kind Code:
B2
Abstract:
PURPOSE:To reduce control burden on a control part which controls the communication processing of data by performing the setting/release of a flag representing the abnormal reception of the data by means of the hardware. CONSTITUTION:The constituting bit of each character data DT transmitted in a start-stop system is stored in a shift register 16 sequentially, and when the storage of all constituting bits is completed, the content of the shift register 16 is transferred to a data latch circuit 17, and, it is read out to the control part which performs the communication control of the data. Succeeding reception data is latched with the data latch circuit 17 before the readout of preceding reception data latched with the latch circuit 17 is completed, and when the abnormal reception of the data occurs, the flag OERR representing the abnormal reception is outputted(flag setting) from an overrun error detection circuit 25, and after that, when the abnormal reception is solved, the flag OERR (flag setting) is stopped(flag release). The control burden on the control part can be reduced by performing the setting/release of the flag OERR by the overrun error detection circuit 25.
Inventors:
Toshihiro Mori
Application Number:
JP11557894A
Publication Date:
November 25, 2002
Filing Date:
May 27, 1994
Export Citation:
Assignee:
Kyocera Mita Corporation
International Classes:
H04N1/32; H04L13/08; H04L25/38; H04L29/06; (IPC1-7): H04L13/08; H04L25/38; H04L29/06; H04N1/32
Domestic Patent References:
| JP5739446A |
Attorney, Agent or Firm:
Etsushi Kotani