Title:
【発明の名称】不揮発性半導体記憶装置
Document Type and Number:
Japanese Patent JP3359615
Kind Code:
B2
Abstract:
A first memory cell block (10a), connected to one input terminal of a sense amplifier (SA0) through a main bit line (MBL0), includes: four memory cells (Ma0) through (Ma3) connected in series together and to word lines (TWL0) through (TWL3), respectively; and a dummy cell (DMa0) connected to a dummy word line (TDWL0). The drains of these memory cells (Ma0) through (Ma3) are connected to a first select gate (TS1) through a sub-bit line (SBL0), and the drain of the dummy cell (DMa0) is also connected to the first select gate (TS1). A second memory cell block (10b), connected to the other input terminal of the sense amplifier (SA0) through a complementary main bit line (MBL1), also includes a dummy cell. (DMb0) connected to the dummy word line (TDWL0).
Inventors:
Takashi Maruyama
Makoto Kojima
Makoto Kojima
Application Number:
JP2000111573A
Publication Date:
December 24, 2002
Filing Date:
April 13, 2000
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
G11C16/04; G11C16/06; G11C16/28; (IPC1-7): G11C16/04; G11C16/06
Domestic Patent References:
| JP27293A | ||||
| JP8203291A | ||||
| JP1011982A | ||||
| JP6290591A |
Attorney, Agent or Firm:
Hiroshi Maeda (1 person outside)