Title:
【発明の名称】半導体素子のチップサイズパッケージ
Document Type and Number:
Japanese Patent JP3360723
Kind Code:
B2
Abstract:
In a chip-size package, an insulator tape is formed with a conductive wire having a wider section which is greater in width than other sections of the wire and a conductive bump connected to the wider section of the wire. The insulator tape is further formed with a first plurality of slits arranged on one side of the wider section of the wire and a second plurality of slits arranged on the other side of the wider section. An integrated circuit chip is provided having a conductive pad connected to the copper bump.
Inventors:
Shohei Okazaki
Yoshihiro Matsumoto
Yoshihiro Matsumoto
Application Number:
JP16082299A
Publication Date:
December 24, 2002
Filing Date:
June 08, 1999
Export Citation:
Assignee:
NEC
International Classes:
H01L23/12; H01L21/60; H01L23/31; H01L23/485; (IPC1-7): H01L23/12
Domestic Patent References:
| JP10340925A | ||||
| JP9321073A | ||||
| JP945809A | ||||
| JP8306739A | ||||
| JP200031630A | ||||
| JP6120300A |
Attorney, Agent or Firm:
Nobuyuki Kaneda (2 others)