Title:
【発明の名称】基板上の構造を平坦化する方法
Document Type and Number:
Japanese Patent JP3361847
Kind Code:
B2
Abstract:
A novel global planarization process is disclosed which is fully compatible with semiconductor processing and which is superior to the existing global planarization methods such as chemical/mechanical polishing (CMP). The process disclosed is called metal melt-solidification planarization (MMSP). A layer of a low melting point/high boiling point metal such as tin or a suitable alloy is deposited on a nonplanar wafer surface via physical-vapor deposition or chemical-vapor deposition or evaporation or plating. The wafer is then heated to above the tin melting point, cooled back to resolidify tin, and etched back to form a globally planar surface.
Inventors:
Mail Dad M. Moslech
Application Number:
JP2957193A
Publication Date:
January 07, 2003
Filing Date:
January 04, 1993
Export Citation:
Assignee:
Texas Instruments Incorporated
International Classes:
H01L21/027; H01L21/3065; H01L21/3105; H01L21/302; H01L21/316; H01L21/3205; H01L21/321; (IPC1-7): H01L21/3065; H01L21/3205
Domestic Patent References:
| JP22619A | ||||
| JP1108747A | ||||
| JP63166246A | ||||
| JP4208529A | ||||
| JP4336450A | ||||
| JP2177355A |
Attorney, Agent or Firm:
Akira Asamura (2 outside)