Title:
【発明の名称】ポリッシュによる平坦化工程を含む電子装置の製造方法
Document Type and Number:
Japanese Patent JP3362397
Kind Code:
B2
Abstract:
In a method of fabricating electronic components of the type wherein trenches formed in a substrate are filled up with a filling material deposited by a deposition process achieving etching and deposition concurrently, the improvement which comprises portions of the filling material deposited on those portion of the substrate other than those corresponding to the trenches are leveled up to the same height by an additional deposition of the filling material, or alternatively by a full-surface etch back process. With this leveling of the deposited material, a subsequent polishing operation can be performed smoothly with high accuracy. During the polishing operation, the resistance between a conductive polish-stop layer on the substrate and a surface of a polishing member contacting the substrate is monitored to determine a polish end.
Inventors:
Junichi Sato
Tetsuo Goujo
Tetsuo Goujo
Application Number:
JP8957391A
Publication Date:
January 07, 2003
Filing Date:
March 28, 1991
Export Citation:
Assignee:
ソニー株式会社
International Classes:
H01L21/76; H01L21/762; H01L21/304; (IPC1-7): H01L21/304; H01L21/76
Domestic Patent References:
| JP1207929A | ||||
| JP4106924A | ||||
| JP3139858A |
Attorney, Agent or Firm:
Toru Takatsuki